The increased use of telephone twisted pair wiring for data communications has resulted in a push for faster modems and improved signaling protocols compatible with the public switched telephone network (“PSTN”). Examples of these improved protocols include a variety of digital subscriber line (“DSL”) communications such as asymmetric digital subscriber line (“ADSL”), symmetric digital subscriber line (“SDSL”), hi-bit rate digital subscriber line (“HDSL”) and very high rate digital subscriber line (“VDSL”). Each DSL variant represents a different transmission speed over a different distance of copper pair wiring.
ADSL offers differing upload and download speeds and can be configured to deliver in excess of eight (8) megabits of data per second (8000K) from the network to the customer. This is more than 120 times faster than dial-up service and 100 times faster than integrated services digital network (“ISDN”). ADSL enables voice and high speed data to be sent simultaneously over the existing telephone line. ADSL uses the existing analog local loop lines for digital data transfer (to and from the remote location). It shares the bandwidth of the local loop with the existing phone system and does not require modification to the central office (“CO”) switch. It is asymmetrical because the upstream transfer rate is slower than the downstream data rate. This means that the data transfer from the remote location to the CO is a different rate than the data transfer rate from the CO to the remote location.
For an ADSL based service, ADSL modems at the CO exchange data through telephone wiring with compatible ADSL modems at remote locations. The ADSL modems at the CO also exchange data with servers. The central office modem is sometimes referred to as an ADSL Transceiver Unit-Central Office or “ATU-C.” The remotely located ADSL modem is sometimes referred to as an ADSL Transceiver UNIT-Remote or “ATU-R.” Any telephone equipment that may be in use at the remote location is connected to the same telephone wiring as the ATU-R. In an ADSL environment, the ATU-R is responsible for loop timing, i.e., synchronizing both its receiver and transmitter to the clock from the CO so that reliable communications can be achieved in both directions between the ATU-C and the ATU-R.
Timing recovery schemes are used to obtain synchronization by altering the sampling frequency and sampling phase to sample the estimated transmitted signal at its peak. Because the frequency of the oscillator at the ATU-R does not exactly match the frequency of the oscillator at the ATU-C, demodulation brings the signal to near baseband with some frequency offset. Timing recovery schemes remove (i.e., compensate for) the frequency offset so that the signal can be processed at baseband.
Almost all of the timing recovery schemes implemented on current ADSL modems use voltage-controlled crystal oscillator (“VCXO”) devices. FIG. 1 diagrammatically illustrates conventional VCXO-based timing recovery, in which the digital side is enclosed in dashed block 170. The clock from VCXO 105 is used as the sampling clock for A/D converter 110, which receives analog signal 101 and converts it to digital, and for D/A converter 115, which transmits analog signal 103. Time domain equalizer (“TEQ”) 125 receives the digital signal from A/D 110 and shortens the length of the channel to less than the length of the cyclic prefix, i.e. it shortens the channel impulse response (“CIR”). Fast Fourier Transform (“FFT”) 130 receives the signal from TEQ 125 and converts the time domain symbols to the frequency domain. Converted signal 133 is then transmitted out of block 170 to frequency domain equalizer (“FEQ”) 150 and within block 170 to phase error extractor 135. Signal 133 is processed successively through FEQ 150, Viterbi decoder 152, deinterleaver 154, RS decoder 156 and descrambler 158 to host microprocessor interface 160 for transmission to host microprocessor 180. A signal sent from microprocessor 180 is processed successively through interface 160, scrambler 162, RS encoder 164, interleaver 166, trellis encoder 168, gain adjuster 170 and Inverse FFT (“IFFT”) 172 for transmission by D/A 115.
Within block 170, phase error extractor 135 extracts phase error signal 137 and feeds signal 137 to Digital Phase Locked Loop (“PLL”) 140. PLL 140 tracks the frequency offset of signal 137, sending the estimated frequency offset as signal 143 to D/A 120 for conversion into an analog signal that is used to control VCXO 105. D/A converters, such as D/A 120, and VCXO devices, such as VCXO 105, are expensive devices. The cost of an ATU-R can be significantly reduced if both the VCXO, such as VCXO 105, and its associated D/A converter, such as D/A 120, can be eliminated. Additionally, VCXO-based timing recovery schemes are generally only capable of tracking a maximum offset of 100 ppm.
It is therefore desirable to provide a solution that eliminates both the VXCO and its associated D/A converter from the timing recovery scheme, thereby significantly reducing manufacturing costs, and that enables tracking of a wider frequency offset. The present invention provides this with a novel timing recovery scheme implemented entirely in the digital domain. Exemplary embodiments of the present invention include a free running clock as the sampling clock for the A/D and D/A converters, and interpolators to correct timing errors for both the receive and transmit samples. The desired sample can be obtained based on its timing offset and its neighboring samples.